• DocumentCode
    1968078
  • Title

    Designing a new encryption method for optimum parallel performance

  • Author

    Posch, K.C. ; Posch, Karl C.

  • Author_Institution
    Inst. for Applied Inf. Process. & Commun., Graz Univ. of Technol., Austria
  • Volume
    2
  • fYear
    1995
  • fDate
    19-21 Apr 1995
  • Firstpage
    849
  • Abstract
    This paper describes the design process from algorithm design to the chip level for a parallel implementation of a modified version of the RSA encryption method. The final system consists of several dozens of custom chips computing module exponentiation based on residue number system coding. Emphasis is put on the hierarchical design view, its benefits and ifs shortcomings
  • Keywords
    cryptography; parallel algorithms; parallel architectures; RSA encryption method; custom chips; encryption method; hierarchical design view; module exponentiation; optimum parallel performance; residue number system coding; Algorithm design and analysis; Concurrent computing; Cryptography; Design methodology; Hardware; Network synthesis; Process design; Shape; Testing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Algorithms and Architectures for Parallel Processing, 1995. ICAPP 95. IEEE First ICA/sup 3/PP., IEEE First International Conference on
  • Conference_Location
    Brisbane, Qld.
  • Print_ISBN
    0-7803-2018-2
  • Type

    conf

  • DOI
    10.1109/ICAPP.1995.472276
  • Filename
    472276
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1968078