Evaluation of the performance and reliability of a 1M SRAM on fully-depleted SOI

Summary form only given. Although there has been a fair amount of work published on fully-depleted SOI, little has been published on the capability of complex ULSI circuits fabricated with this technology. In this paper, we discuss the performance of a 1M SRAM fabricated on fully depleted SOI and compare it to the same design built with an epi/bulk process. Reliability effects are also examined. The 1M SRAM used was a design optimized for a radiation-hardened 3.3 V/0.5 /spl mu/m bulk production process. This radiation-hardened design has a cell size of 89 /spl mu/m/sup 2/ and a chip size of 11.6/spl times/12.0 mm. There are over 7 million transistors on the chip. This 1M SRAM design, unchanged, was built on fully-depleted SOI substrates. Fully-depleted SOI requires no body ties for SEU hardening, making a direct design mapping viable. The SOI version of this 1M SRAM was built without the cross-coupled intracell polysilicon resistors that are used in the bulk design to enhance SEU hardness.