1 GHz fully pipelined 3.7 ns address access time 8 k/spl times/1024 embedded DRAM macro

Author

Takahashi, O. ; Dhong, S. ; Ohkubo, M. ; Onishi, S. ; Dennard, R. ; Hannon, R. ; Crowder, S. ; Iyer, S. ; Wordeman, M. ; Davari, B. ; Weinberger, W.B. ; Aoki, N.

Author_Institution

IBM Corp., Austin, TX, USA

fYear

2000

fDate

9-9 Feb. 2000

Firstpage

396

Lastpage

397

Abstract

This macro is designed as a DRAM cache for a future gigahertz microprocessor system based on a logic-based DRAM technology. The most notable feature of this macro is its ability to run synchronously with a gigahertz CPU clock in a fully-pipelined fashion. It operates with a 1 GHz clock signal at 85/spl deg/C, nominal process parameters, and a 10% degraded V/sub DD/. The design is fully pipelined and synchronous with 16 independent subarrays. The address access time is 3.7 ns, four cycles with a 1 GHz clock. The subarray cycle time is 12 ns.

Keywords

DRAM chips; cache storage; cellular arrays; embedded systems; pipeline processing; 1 GHz; 3.7 ns; DRAM cache; embedded DRAM macro; fully pipelined; independent subarrays; logic-based DRAM technology; state machine implementation; synchronous design; Bidirectional control; CMOS technology; Clocks; Degradation; High definition video; Laboratories; Microelectronics; Microprocessors; Random access memory; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-5853-8

Type

conf

DOI

10.1109/ISSCC.2000.839831

Filename

839831