Title :
A 16 MB cache DRAM LSI with internal 35.8 GB/s memory bandwidth for simultaneous read and write operation
Author :
Nakayama, M. ; Sakakibara, H. ; Kusunoki, Masataka ; Kurita, K. ; Yokoyama, Y. ; Miyaoka, S. ; Koike, J. ; Tamba, N. ; Kobayashi, T. ; Kume, M. ; Sawamoto, H. ; Kawata, Akihiro ; Tanaka, H. ; Takada, Y. ; Yamamoto, M. ; Yagyu, M. ; Tsuchiya, Y. ; Yoshida,
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
With continuous scaling of process technology, embedded DRAM technology becomes promising for high performance cache memory systems because of its potential of large memory capacity and high bandwidth. Although several papers reported, none of them has enough memory bandwidth or capacity for high-end computer applications. This 16 MB cache DRAM LSI chip with internal 35.8 GB/s memory bandwidth and 9.0 ns DRAM random access latency uses merged logic DRAM process technology that combines leading-edge DRAM devices equivalent to that of 256 Mb conventional DRAM with high-speed 0.2 /spl mu/m CMOS logic.
Keywords :
CMOS logic circuits; DRAM chips; cache storage; cellular arrays; embedded systems; large scale integration; 0.2 micron; 16 MB; 35.8 Gbit/s; SPICE simulation; cache DRAM LSI; clock distribution; embedded DRAM technology; high bandwidth; high performance cache memory; high-end computer applications; high-speed CMOS logic; large memory capacity; macro function; merged logic DRAM process technology; random access latency; simultaneous read/write operation; Bandwidth; CMOS logic circuits; CMOS process; CMOS technology; Cache memory; Computer applications; Delay; Large scale integration; Logic devices; Random access memory;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839832
