Title :
A 450 MHz 64 b RISC processor using multiple threshold voltage CMOS
Author :
Yamashita, T. ; Yoshida, N. ; Sakamoto, M. ; Matsumoto, T. ; Kusunoki, M. ; Takahashi, H. ; Wakahara, A. ; Ito, T. ; Shimizu, T. ; Kurita, K. ; Higeta, K. ; Mori, K. ; Tamba, N. ; Kato, N. ; Miyamoto, K. ; Yamagata, R. ; Tanaka, H. ; Hiyama, T.
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
A 450 MHz 64 b RISC processor die contains 8.3 M logic-gate transistors and 20 M RAM transistors. 0.25 /spl mu/m CMOS with 0.2 /spl mu/m Lg, 4 nm tox, 1.8 V Vdd, and 7-layer metal technology is used. Multiple-threshold-voltage design with minimum standby current is introduced. Previously-reported application of this technique is to limited to static circuits. Here it is applied not only to static circuits, but also to clock-distribution drivers, register files and dynamic circuits in RAM macros. Precise clock-skew control, PLL jitter minimization, and optimized buffer insertion on long wires are carried out in accordance with the critical path analysis.
Keywords :
CMOS digital integrated circuits; microprocessor chips; reduced instruction set computing; 0.25 micron; 1.8 V; 450 MHz; 64 bit; CMOS chip; PLL jitter minimization; RAM macro; RISC processor; buffer insertion optimization; clock distribution driver; clock skew control; critical path analysis; dynamic circuit; multiple threshold voltage design; register file; standby current; static circuit; CMOS process; CMOS technology; Clocks; Driver circuits; Jitter; Minimization; Phase locked loops; Reduced instruction set computing; Registers; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839839
