4 Gb/s GaAs gate arrays with 0.5 mu m WSi-gate MESFET technology

Author

Hirayama, H. ; Saito, H. ; Kishi, K. ; Hosono, Y. ; Tsuchiya, T. ; Setoyama, Y. ; Kanamori, M. ; Tanaka, Y. ; Uetake, K. ; Furutsuka, T.

Author_Institution

NEC Corp., Kawasaki, Japan

fYear

1989

fDate

22-25 Oct. 1989

Firstpage

325

Lastpage

328

Abstract

GaAs 200-gate and 500-gate arrays operating at up to 4 Gb/s have been successfully developed using 0.5- mu m WSi-gate MESFET technology. The arrays had emitter coupled logic (ECL)-compatible interfaces and -2/-3.5-V or -2/-4.5-V power supply voltage and were composed of mask-programmable four-input NOR gates, implemented with a one-diode BFL circuit. The unloaded delay times were 35 ps/gate for the 200-gate arrays and 44 ps/gate for the 500-gate arrays. The maximum operating speeds of the test circuits were 4.6 Gb/s for a 4 bit 2-to-1 multiplexer (MUX), more than 5 Gb/s for a 4-bit 1-to-2 demultiplexer (DEMUX), and 3.6 Gb/s for a 4-to-1 MUX. ECL level compatibilities were successfully obtained at up to 4 Gb/s.<>

Keywords

III-V semiconductors; Schottky gate field effect transistors; field effect integrated circuits; logic arrays; logic gates; 0.5 micron; 4 Gbit/s; GaAs; MESFET technology; WSi gate; demultiplexer; emitter coupled logic; gate arrays; mask-programmable four-input NOR gates; maximum operating speeds; multiplexer; one-diode BFL circuit; power supply voltage; unloaded delay times; Circuit testing; Coupling circuits; Delay; Gallium arsenide; Logic arrays; Logic circuits; MESFETs; Multiplexing; Power supplies; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1989. Technical Digest 1989., 11th Annual

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/GAAS.1989.69353

Filename

69353