A slicing-floorplan algorithm implementation for VLSI design

This paper describes a floorplan design approach that combines both a heuristic graph bipartitioning procedure and a slicing tree representation in the physical design of VLSI systems. The description of the circuit to be floorplanned contains a set of functional modules each having a number of possible dimensions and a net-list containing the connectivity information. The slicing tree representation provides an efficient free traversal operations using recursion for obtaining area-efficient floorplans. The slicing paradigm also eliminates the cyclical conflicts in module placement and hence ensures better routability