Title :
A CMOS quaternary threshold logic full adder circuit with transparent latch
Author :
Current, K. Wayne
Author_Institution :
Dept. of Electr. Eng., California Univ., Davis, CA, USA
Abstract :
A circuit that realizes the quaternary threshold logic full adder function with transparent latching has been realized in a standard polysilicon-gate CMOS technology. In its FOLLOW mode, the quaternary full adder accepts two quaternary inputs and a binary CARRY input, and develops a two-quaternary-digit output word that is the base-four sum of the inputs. In the HOLD mode, these output states are held by the transparent multiple-valued latch subcircuit. The circuit is presented and its experimental performance described
Keywords :
logic circuits; many-valued logics; threshold logic; full adder circuit; polysilicon-gate CMOS; quaternary threshold logic; transparent latch; Adders; Artificial neural networks; CMOS logic circuits; CMOS technology; Circuit noise; Latches; Multivalued logic; Read only memory; Signal processing; Very large scale integration;
Conference_Titel :
Multiple-Valued Logic, 1990., Proceedings of the Twentieth International Symposium on
Conference_Location :
Charlotte, NC
Print_ISBN :
0-8186-2046-3
DOI :
10.1109/ISMVL.1990.122616
