DocumentCode
1968796
Title
Design methodology for chip-on-chip applications
Author
Low, Yee L. ; Frye, Robert C. ; O´Connor, K.J.
Author_Institution
Bell Labs., Lucent Technol., Murray Hill, NJ, USA
fYear
1997
fDate
27-29 Oct. 1997
Firstpage
5
Lastpage
8
Abstract
We describe a design methodology for several chip-on-chip applications that uses a single redistribution metal layer on each chip and solder bumps as vias to form a two-level routing system.
Keywords
integrated circuit design; integrated circuit packaging; multichip modules; network routing; MCM; chip-on-chip packaging; design methodology; single redistribution metal layer; solder bumps; two-level routing system; vias; Costs; Design methodology; Integrated circuit interconnections; Integrated circuit packaging; Logic circuits; Logic devices; Microprocessors; Multichip modules; Routing; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 1997., IEEE 6th Topical Meeting on
Conference_Location
Austin, TX
Print_ISBN
0-7803-8649-3
Type
conf
DOI
10.1109/EPEP.1997.634024
Filename
634024
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