Binary to quaternary encoding in clocked CMOS circuits using weak buffer

A binary-to-quaternary encoder is presented for four-valued signaling of buses in clocked CMOS integrated circuits. It uses a new CMOS circuit called the weak buffer. A weak buffer takes a conventional binary input and produces two stable output voltage levels of intermediate magnitudes that lie between the conventional 0 and 1 levels for binary circuits. Thus, the conventional binary voltage levels and the output levels of the weak buffer constitute a set of quaternary logic values. The encoder uses a binary-to-quaternary mapping different from the mappings used by other such encoder designs. Use of the new mapping and the weak buffer leads to 30%-56% savings in transistor count compared with previously reported designs. SPICE simulation results verifying its operation are presented. It is fairly insensitive to small variations in process parameters, and hence suitable for practical use. The circuit has been layed out using MAGIC and has been submitted to MOSIS for fabrication