• DocumentCode
    1969017
  • Title

    Delta-I noise avoidance methodology for high performance chip designs [CMOS microprocessors]

  • Author

    Cases, Moises ; Singh, Bhupindra ; Smith, Howard

  • Author_Institution
    IBM Corp., Austin, TX, USA
  • fYear
    1997
  • fDate
    27-29 Oct. 1997
  • Firstpage
    27
  • Lastpage
    30
  • Abstract
    A methodology which controls induced di/dt noise for high performance chip designs is described. Delta-I modeling and analysis for the chip, module and card is used to define a strategy and effectiveness of various decoupling schemes over a broad frequency range.
  • Keywords
    CMOS digital integrated circuits; integrated circuit design; integrated circuit modelling; integrated circuit noise; microprocessor chips; CMOS microprocessors; IC noise modeling; chip design; decoupling schemes; delta-I noise; induced di/dt noise; CMOS technology; Capacitors; Circuit noise; Design methodology; Frequency; Noise generators; Packaging; Power supplies; Switching circuits; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Performance of Electronic Packaging, 1997., IEEE 6th Topical Meeting on
  • Conference_Location
    Austin, TX
  • Print_ISBN
    0-7803-8649-3
  • Type

    conf

  • DOI
    10.1109/EPEP.1997.634030
  • Filename
    634030
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1969017