DocumentCode
1969332
Title
A New Greedy Algorithm for VLSI Floorplan Optimization
Author
Tang, Maolin
Author_Institution
Fac. of Inf. Technol., Queensland Univ. of Technol., Brisbane, QLD
Volume
4
fYear
2008
fDate
12-14 Dec. 2008
Firstpage
1126
Lastpage
1129
Abstract
A very large scale integrated-circuit (VLSI) floorplan can be represented in an ordered tree (O-tree), and therefore the VLSI floorplan optimization problem can be transformed into an O-tree permutation problem. This paper presents a new greedy O-tree permutation algorithm and applies it to the VLSI floorplan optimization problem.
Keywords
VLSI; circuit complexity; circuit optimisation; greedy algorithms; integrated circuit layout; trees (mathematics); VLSI floorplan optimization; circuit complexity; greedy algorithm; ordered tree permutation problem; very large scale integrated circuit; Algorithm design and analysis; Computational complexity; Computer science; Costs; Equations; Greedy algorithms; Information technology; Software engineering; Very large scale integration; Wire; VLSI; floorplanning; greedy algorithm; optimization; ordered tree;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Science and Software Engineering, 2008 International Conference on
Conference_Location
Wuhan, Hubei
Print_ISBN
978-0-7695-3336-0
Type
conf
DOI
10.1109/CSSE.2008.1560
Filename
4722817
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