Decap aware sleep transistor design

Multithreshold CMOS (MTCMOS) has been a proven methodology to reduce leakage power in DSM designs. Previously lumped sleep transistors were designed for worst case condition, and hence occupied a large area. To reduce the area, cluster based sleep transistor design was proposed which takes into account simultaneous switching within the circuit blocks. In this paper, we propose an improved method of clustering the sleep transistors by taking on chip decoupling capacitances into account. With the proposed heuristic, we are able to obtain sleep transistor area reduction of 64% with respect to conventional clustering methodology. The leakage current reduction for the circuit blocks is in the order of 2000X to 8000X with respect to the ones without sleep transistors. We also analyze the effect of the sleep transistor width on the wake-up time of the circuit blocks, which can be used effectively during system design. The experimental results are shown for ISCAS´85 benchmarks.