Control system architecture: the standard and nonstandard models

Control system architecture development has followed the advances in computer technology through mainframes to minicomputers to micros and workstations. This technology advance and increasingly challenging accelerator data acquisition and automation requirements have driven control system architecture development. In summarizing the progress of control system architecture at the last International Conference an Accelerator and Large Experimental Physics Control Systems (ICALEPCS) B. Kuiper (1991) asserted that the system architecture issue was resolved and presented a “standard model”. The “standard model” consists of a local area network (Ethernet or FDDI) providing communication between front end microcomputers, connected to the accelerator, and workstations, providing the operator interface and computational support. Although this model represents many present designs, there are exceptions including reflected memory and hierarchical architectures driven by requirements for widely dispersed, large channel count or tightly coupled systems. This paper describes the performance characteristics and features of the “standard model” to determine if the requirements of “non-standard” architectures can be met. Several possible extensions to the “standard model” are suggested including software as well as the hardware architectural features