Control of off-state current in scaled PD/SOI CMOS digital circuits

A recent study of the scalability of partially depleted (PD) SOI CMOS technology (Chau et al. IEEE IEDM Tech. Dig., p. 591, Dec. 1997) led to the conclusion that it was no better than bulk-Si CMOS for sub-0.25 /spl mu/m digital applications, irrespective of its inherent advantages, because of the higher threshold voltage (V/sub T/) needed to limit the off-state current (I/sub off/) of the nMOSFET, which tends to be high because of the drain (V/sub DS/)-induced floating-body (FB) effect (i.e. the kink effect) in addition to the barrier lowering (DIBL). In this paper, we give a physically insightful analysis of the FB effect on I/sub off/ based on the scaled PD/SOI CMOS technology described by Chau et al. which contradicts the negative assessment of the scalability of SOI digital ICs. Device and circuit simulations of operation at high chip temperatures (55-85/spl deg/C) that are typical for high-performance circuits show that the FB effect can be naturally ameliorated, and that previously proven techniques for controlling FB effects are also effective in limiting I/sub off/. Furthermore, we show that the temperature coefficient of the body-source voltage (V/sub BS/) is strongly dependent on the recombination current (I/sub R/) of the junctions, and the impact on circuit performance of an increased I/sub R/ is shown to be negligible.