Layout-oriented synthesis of high performance analog circuits

Author

Dessouky, Mohamed ; Louërat, Marie-Minerve ; Porte, Jacky

Author_Institution

Lab. LIP6, Paris VI Univ., France

fYear

2000

fDate

2000

Firstpage

53

Lastpage

57

Abstract

This paper presents a methodology for the synthesis of high performance analog circuits. Layout parasitics are estimated and compensated during circuit sizing. Physical layout constraints are thus taken into consideration early in the design. This approach shortens the overall design time by avoiding laborious sizing-layout iterations. The approach has been implemented using two knowledge-based tools dedicated to analog circuit sizing and layout generation. An example of a high performance OTA is presented to illustrate the effectiveness of the approach

Keywords

analogue integrated circuits; circuit layout CAD; integrated circuit layout; knowledge based systems; monolithic integrated circuits; OTA design; analog circuit layout generation; analogue circuit sizing; high performance analog circuits; knowledge-based tools; layout parasitics estimation; layout-oriented synthesis; parasitics compensation; physical layout constraints; Analog circuits; Automatic control; Circuit optimization; Circuit synthesis; Coupling circuits; Degradation; Design optimization; Electrical capacitance tomography; Parasitic capacitance; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings

Conference_Location

Paris

Print_ISBN

0-7695-0537-6

Type

conf

DOI

10.1109/DATE.2000.840015

Filename

840015