Title :
Fast evaluation of sequence pair in block placement by longest common subsequence computation
Author :
Tang, Xiaoping ; Ruiqi Tian ; Wong, D.F.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Abstract :
Murata et al. (1996) introduced an elegant representation of block placement called sequence pair. All block placement algorithms which are based on sequence pairs use simulated annealing where the generation and evaluation of a large number of sequence pairs is required. Therefore, a fast algorithm is needed to evaluate each generated sequence pair, i.e. to translate the sequence pair to its corresponding block placement. This paper presents a new approach to evaluate a sequence pair based on comparing longest common subsequence in a pair of weighted sequences. We present a very simple and efficient O(n2) algorithm to solve the sequence pair evaluation problem. We also show that using a more sophisticated data structure, the algorithm can be implemented to run in O(n log n) time. Both implementations of our algorithm are significantly faster than the previous O(n2) graph-based algorithm. For example, we achieve 60× speedup over the previous algorithm when input size n=128
Keywords :
VLSI; circuit complexity; circuit layout CAD; circuit optimisation; integrated circuit layout; network topology; sequences; simulated annealing; VLSI complexity; block placement; constraint graphs; fast sequence pair evaluation; longest common subsequence computation; optimal floorplanning; pair of weighted sequences; simulated annealing; topology representation; Costs; Data structures; Integrated circuit interconnections; Integrated circuit technology; Simulated annealing; Transistors; Very large scale integration;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-0537-6
DOI :
10.1109/DATE.2000.840024