• DocumentCode
    1970761
  • Title

    LDMOS Capacitance Analysis versus Gate and Drain Biases, Based on Comparison between TCAD Simulations and Measurements

  • Author

    Frre, S.F. ; Rhayem, J. ; Adawe, H.O. ; Gillon, R. ; Tack, M. ; Walton, A.J.

  • Author_Institution
    Alcatel Microelectronics, Oudenaarde, Belgium and The University of Edinburgh, UK
  • fYear
    2001
  • fDate
    11-13 September 2001
  • Firstpage
    219
  • Lastpage
    222
  • Keywords
    Analytical models; Capacitance measurement; Microelectronics; Performance evaluation; Power system dynamics; Power system modeling; Scattering parameters; Shape measurement; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Device Research Conference, 2001. Proceeding of the 31st European
  • Print_ISBN
    2-914601-01-8
  • Type

    conf

  • DOI
    10.1109/ESSDERC.2001.195240
  • Filename
    1506622
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1970761