DocumentCode
1970971
Title
Memory-Conscious Reliable Execution on Embedded Chip Multiprocessors
Author
Chen, G. ; Kandemir, M. ; Kolcu, I.
Author_Institution
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA
fYear
2006
fDate
25-28 June 2006
Firstpage
13
Lastpage
22
Abstract
Code and data duplication has been identified as one of the important mechanisms for improving reliability. In a chip multiprocessor-based execution environment, while it is possible to hide the overhead of code duplication through parallelism, hiding the memory space overhead incurred by data duplication is more difficult. This paper presents a compiler-directed memory-conscious data duplication scheme that tries to minimize the extra memory space required by duplicate execution. The proposed approach achieves this goal by using the memory locations that hold dead data to store the duplicates of the actively-used data. In this way, instead of using extra memory storage for duplicate elements, we use the existing memory locations to the extent allowed by usage patterns of data. The results collected from our experiments clearly show that the proposed approach saves significant memory space, as compared to a straightforward approach that implements full duplication
Keywords
computer architecture; embedded systems; microprocessor chips; multiprocessing systems; program compilers; CMP architecture; code duplication; compiler-directed memory-conscious data duplication scheme; embedded chip multiprocessor-based execution environment; extra memory storage; memory-conscious reliable execution; Computer architecture; Computer science; Data engineering; Embedded computing; Network-on-a-chip; Optimizing compilers; Parallel processing; Reliability engineering; Silicon; Sun;
fLanguage
English
Publisher
ieee
Conference_Titel
Dependable Systems and Networks, 2006. DSN 2006. International Conference on
Conference_Location
Philadelphia, PA
Print_ISBN
0-7695-2607-1
Type
conf
DOI
10.1109/DSN.2006.51
Filename
1633491
Link To Document