Design of High-Linearity Amplifier for Wireless LAN Transceiver

Author

Nizhnik, O. ; Pokharel, R.K. ; Kanaya, H. ; Yoshida, K.

Author_Institution

Grad. Sch. of Inf. Sci. & Electr. Eng., Kyushu Univ., Fukuoka

fYear

2007

fDate

11-14 Dec. 2007

Firstpage

1

Lastpage

4

Abstract

High third-order intercept output point (OIP3) RF amplifier, suitable for cheap semiconductor technology is proposed. The circuit functionality simulated using Agilent ADS and parasitic components were taken into account using Assura RCX chip design software. Chip has designed for TSMC 0.35-um BiCMOS process. An OIP3 over +30 dBm was achieved with a gain of 8 dB, noise figure 5 dB, and a power consumption 80 mW. Amplifier is intended to be used in receiver and transmitter paths of the 802.11 a/b/n wireless LAN front-end in 5 GHz band.

Keywords

BiCMOS integrated circuits; radiofrequency amplifiers; transceivers; wireless LAN; Agilent ADS; Assura RCX chip design software; BiCMOS process; frequency 5 GHz; gain 8 dB; high-linearity amplifier; parasitic component; power 80 mW; wireless LAN transceiver; BiCMOS integrated circuits; Chip scale packaging; Circuit simulation; Energy consumption; Gain; Noise figure; Radiofrequency amplifiers; Software design; Transceivers; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 2007. APMC 2007. Asia-Pacific

Conference_Location

Bangkok

Print_ISBN

978-1-4244-0748-4

Electronic_ISBN

978-1-4244-0749-1

Type

conf

DOI

10.1109/APMC.2007.4554554

Filename

4554554