DocumentCode
1971064
Title
Implementation of an optimal parallel algorithm for arithmetic expression parsing
Author
Suresh, Hungenahally
Author_Institution
Fac. of Sci. & Technol., Griffith Univ., Brisbane, Qld., Australia
Volume
2
fYear
1995
fDate
19-21 Apr 1995
Abstract
Development of efficient algorithms for parallel computer architectures is an on-going research area and in the recent past a great volume of theoretical work has been carried out for the search of suitable algorithms in concurrent processing environment. In this paper, the results obtained in the implementation of an Optimal Parallel Algorithm developed by Deng and Iyengar (1992) in the esoteric area of arithmetic expression parsing is reported. The `C´ code developed and tested on an IBM Compatible Personal Computer in this investigative study, is a simple recursive descent parser and may be used for parallel parsing of arithmetic expressions. The algorithm was developed to suit the SIMD parallel architecture to avoid any communication bottlenecks posed by PVM system, however, design and structure of the code readily permits portability to a parallel computer system
Keywords
digital arithmetic; parallel algorithms; parallelising compilers; PVM; SIMD parallel architecture; arithmetic expression parsing; concurrent processing environment; optimal parallel algorithm; parallel computer architectures; simple recursive descent parser; Australia; Computer architecture; Concurrent computing; Digital arithmetic; Intelligent systems; Microcomputers; Parallel algorithms; Parallel processing; Signal processing algorithms; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Algorithms and Architectures for Parallel Processing, 1995. ICAPP 95. IEEE First ICA/sup 3/PP., IEEE First International Conference on
Conference_Location
Brisbane, Qld.
Print_ISBN
0-7803-2018-2
Type
conf
DOI
10.1109/ICAPP.1995.472290
Filename
472290
Link To Document