An ultra-low-power self-biased current reference

Author

Camacho-Galeano, E.M. ; Galup-Montoro, Carlos ; Schneider, Màrcio Cherern

Author_Institution

Integrated Circuits Lab., Univ. of Santa Catarina, Florianopolis, Brazil

fYear

2004

fDate

7-11 Sept. 2004

Firstpage

147

Lastpage

150

Abstract

This paper presents the design of an ultra-low-power self-biased 400 pA current source. An efficient design methodology has resulted in a cell area around 0.045 mm² (0.027 mm²) in the AMIS 1.5 μm (TSMC 0.35 μm) CMOS technology and power consumption around 2 nW for 1.2 V supply. Simulated and experimental results validate the design and show that the current sources can operate at supply voltages down to 1.1 V with a good regulation (<4%/V variation of the supply voltage in a 0.35 μm technology). This current source is suitable for very-low-power applications.

Keywords

CMOS integrated circuits; MOSFET; circuit simulation; integrated circuit design; low-power electronics; network topology; power consumption; 0.35 micron; 1.1 V; 1.2 V; 1.5 micron; 400 PA; AMIS CMOS technology; MOSFET; circuit simulation; power consumption; topology; ultra low power self-biased current source; CMOS technology; Design methodology; Energy consumption; Integrated circuit technology; Laboratories; Low voltage; MOSFET circuits; Permission; Resistors; Thermal resistance;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2004. SBCCI 2004. 17th Symposium on

Print_ISBN

1-58113-947-0

Type

conf

DOI

10.1109/SBCCI.2004.240769

Filename

1360560