Title :
A yield model for the evaluation of topologically constrained chip architectures
Author :
Ciciani, B. ; Iazeolla, G.
Author_Institution :
Dept. of Electron. Eng., Rome II Univ., Italy
Abstract :
Conventional M-out-of-N yield models can only roughly represent many practical chip architectures. On the other hand, representative models have the drawback of computational complexity. A yield model is introduced that overcomes the limits of existing models and provides ease of computation and predictability in approximation levels. The model is versatile enough to be included in CAM/CAD programming environments. Some application examples are given to illustrate the model accuracy, ease of use, and flexibility
Keywords :
VLSI; circuit CAD; integrated circuit manufacture; CAM/CAD programming environments; approximation levels; topologically constrained chip architectures; yield model; Circuit faults; Computer architecture; Logic circuits; Mathematical model; Predictive models; Programming environments; Reconfigurable logic; Redundancy; Semiconductor device manufacture; State-space methods;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63405
