DocumentCode
1971509
Title
Enhanced 32-bit carry look-ahead adder using multiple output enable-disable CMOS differential logic
Author
Osorio, Mario C B ; Sampaio, Carlos A. ; Reis, Andre I. ; Ribas, Renato P.
Author_Institution
Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil
fYear
2004
fDate
7-11 Sept. 2004
Firstpage
181
Lastpage
185
Abstract
This paper presents an enhanced 32-bit carry look-ahead (CLA) adder implemented using the multi-output enable/disable CMOS differential logic (MOECDL) style. The MOECDL structure proposed represents a promising technique for iterative networks and self-timed circuits. The recursive property of CLA algorithm has been efficiently exploited to demonstrate the advantages of multiple-output structures. The 32-bit MOECDL CLA circuit has been designed into a standard 0.5 μm CMOS technology. Comparison to the known DCVS style is presented through electrical simulation.
Keywords
CMOS logic circuits; SPICE; adders; circuit simulation; 0.5 micron; 32 bit; electrical simulation; enchanced carry look ahead adder; iterative networks; multiple output enable-disable CMOS differential logic; recursive properties; self timed circuits; Adders; Arithmetic; CMOS logic circuits; CMOS technology; Circuit topology; Costs; Logic circuits; Permission; Rails; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Circuits and Systems Design, 2004. SBCCI 2004. 17th Symposium on
Print_ISBN
1-58113-947-0
Type
conf
DOI
10.1109/SBCCI.2004.240872
Filename
1360566
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