FPGA implementation of parallel turbo-decoders

Wireless communication penetrates more and more areas of our everyday lives. Turbo-codes provide good forward-error correction to improve the data transfer reliability. They are used in current standards and future system designers considers them promising candidates. Dedicated hardware, however, is too expensive to use in a new and still rapidly changing system; due to the nonrecurring engineering and mask costs. In this paper, we therefore present a scalable turbo-decoder architecture targeted towards FPGA implementation for low-volume devices. It allows to optimally exploit the given hardware resources on FPGA to match the desired system throughput. Our design is ported to the Xilinx Virtex-II family. On the Virtex-II 3000, we achieve a maximum throughput of 26 Mbit/s at 84 MHz with a latency of 185 μs.