DocumentCode
1971640
Title
Flip-chip redistribution layer electrical characterization and SSO noise simulation
Author
Wu, Zhonghua ; Siguenza, Oscar
Author_Institution
Mainstream Appl., LSI Logic Corp., Milpitas, CA, USA
fYear
1997
fDate
27-29 Oct. 1997
Firstpage
117
Lastpage
120
Abstract
Electrical characterization of flip-chip redistribution layer and detailed study of the associated ohmic drop, simultaneous switching output (SSO) noise and crosstalk are presented. Noise margins are analyzed and design rules are generated based on the simulation.
Keywords
circuit noise; crosstalk; equivalent circuits; flip-chip devices; packaging; switching; SSO noise; cascaded RLC model; crosstalk; design rules; electrical characterization; flip-chip redistribution layer; noise margins analysis; noise simulation; ohmic drop; simultaneous switching output noise; Bonding; Circuit noise; Circuit simulation; Crosstalk; Inductance; Packaging; Parasitic capacitance; Power system modeling; RLC circuits; Solid modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 1997., IEEE 6th Topical Meeting on
Conference_Location
Austin, TX
Print_ISBN
0-7803-8649-3
Type
conf
DOI
10.1109/EPEP.1997.634052
Filename
634052
Link To Document