Recent advances in dielectric breakdown of modern gate dielectrics

Author

Wu, E.Y. ; Suñe, Jordi

Author_Institution

Syst. & Technol. Group, IBM Semicond. R&D Center, Essex Junction, VT, USA

fYear

2013

fDate

13-17 Oct. 2013

Firstpage

5

Lastpage

10

Abstract

In this talk, we first review the first BD and post BD statistics of high-k/SiO₂ bilayer films (or high-κ stacks) by delineating similarities and differences from SiO₂ single-layer films. Then, we will discuss the recent progress on TDDB voltage and temperature dependence in a two-step model of species-release and reaction process. This model is found to be applicable to both SiO₂ and high-κ stacks (pFET inversion mode) and provide a sound physical picture for overall BD process. Finally, we will highlight the challenges in AC TDDB reliability, specifically related to nFET inversion mode of high-k stacks.

Keywords

electric breakdown; field effect transistors; semiconductor device breakdown; silicon compounds; SiO₂; TDDB voltage; bilayer films; dielectric breakdown; high-κ stacks; modern gate dielectrics; nFET; pFET; single-layer films; Acceleration; Data models; Dielectrics; High K dielectric materials; Logic gates; Stress; Temperature dependence;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Reliability Workshop Final Report (IRW), 2013 IEEE International

Conference_Location

South Lake Tahoe, CA

ISSN

1930-8841

Print_ISBN

978-1-4799-0350-4

Type

conf

DOI

10.1109/IIRW.2013.6804141

Filename

6804141