Stress and distortion behavior for VLSI steady state thermal analysis

Stress and distortion behavior is crucial during development of the VLSI (very large scale integration) and WSI (wafer scale integration) circuits for their safe operation. The thermal design aspect remains a major obstacle in front the most required performances of the electronic systems: increase of the speed operation and the components miniaturization. In both cases those results by junction overheating and associated induced higher thermal stress. The design of a reliable large and powerful processor requires the whole device coupled fluid-heat transfer thermal analysis from junction to ambient. In this case, device electro thermal behavior is principally influenced by geometry package, junction structure, and physical heat sources distribution. This paper presents stress and distortion behavior in VLSI and WSI microelectronic devices. A numerical example is given to demonstrate the critical behavior of BGA (ball grid array) package. Its concern the steady state thermal stress and distortion modeling of semiconductor devices undergoing large power heating. A three-dimensional finite element model was constructed to simulate in deep multilevel devices under large power loading. The temperature distributions obtained were used as input in order to compute thermal stress and mechanical deformations of VLSI structures. Based on the FEM (finite element method) the method used combines fluid flow and heat transfer mechanism to predict, in general, working temperature and associated stress and distortion of IC (integrated circuit). In addition, the effect of power density, heat sink characteristics, during thermal response is analyzed. The methodology presented can be used for accurate rating of semiconductor devices or heat sink systems during large ASIC (application specific integrated circuit) circuit design.