Implementing a high performance scheduling discipline WF2Q+ in FPGA

Every server uses a scheduling discipline to decide the order in which the requests are to be served. A scheduling discipline should satisfy the following requirements: 1) it is easy to be implemented; 2) provides fairly distributed bandwidth to competing requests; 3) guarantees performance bounds for a wide range of traffic types; and 4) allows easy admission control decision. To date, a lot of scheduling disciplines have been proposed in the research literature, among which, the strict priority (SP), weighted fair queuing (WFQ) and weight round robin (WRR) are perhaps the three most widely adopted disciplines. However, the generalized processor sharing (GPS) discipline for packet scheduling best caters to the above properties. GPS uses an idealized fluid model that can´t be precisely implemented in the real scenario. Worst case fair weighted fair queuing (WF2Q) is the closest packet approximation algorithm of the GPS discipline. WF2Q+ is an enhanced version of WF2Q and has a less time complexity. This paper first reviews the theory of WF2Q+, simplifies it for our implementation and then presents its detailed implementation in FPGA.