A study on the VLSI implementation of ECC for embedded DRAM

ECC circuitry is an effective on-line method for increasing the reliability and fault tolerance of high density DRAM. Code length, code type and implementation method affect delay and area penalty due to ECC. Four SEC-DED Hsiao codes: (39,32), (72,64), (137,128) and (266,256), are investigated in this paper. We look at the effect of word length on P(error), and compare XOR-tree based and LUT-based implementations. Simulation results show that an LUT structure outperforms the XOR-tree structure in error-correction speed in most cases, although it usually generates a larger area penalty. Our results can be used as a guide for selecting the proper code and implementation method for use in error- corrected DRAM.