DocumentCode
1973272
Title
Architectures and design considerations of CMOS charge pumps for phase-locked loops
Author
El-Hage, Mohamad ; Yuan, Fei
Author_Institution
Dept. of Electr. & Comput. Eng., Ryerson Univ., Toronto, Ont., Canada
Volume
1
fYear
2003
fDate
4-7 May 2003
Firstpage
223
Abstract
A comprehensive review of the architectures of CMOS charge pumps for phase-locked loops and an in-depth comparison of their characteristics, such as speed, minimum supply voltage, mismatch-induced errors, charge injection and clock feed-through induced error´s, and noise rejection, are presented. These charge pumps arc implemented in a 0.13μ CMOS technology and analyzed using Spectre. Simulation results are presented.
Keywords
CMOS integrated circuits; phase locked loops; 0.13 micron; CMOS charge pumps; CMOS circuits; CMOS technology; Spectre; phase-locked loops; Charge pumps; Circuit noise; Clocks; Computer errors; Delay; MOSFETs; Phase frequency detector; Phase locked loops; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on
ISSN
0840-7789
Print_ISBN
0-7803-7781-8
Type
conf
DOI
10.1109/CCECE.2003.1226383
Filename
1226383
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