DocumentCode
1973375
Title
Efficiently Scheduling Multi-Core Guest Virtual Machines on Multi-Core Hosts in Network Simulation
Author
Yoginath, Srikanth B. ; Perumalla, Kalyan S.
Author_Institution
Oak Ridge Nat. Lab., Oak Ridge, TN, USA
fYear
2011
fDate
14-17 June 2011
Firstpage
1
Lastpage
9
Abstract
Virtual machine (VM)-based simulation is a method used by network simulators to incorporate realistic application behaviors by executing actual VMs as high-fidelity surrogates for simulated end-hosts. A critical requirement in such a method is the simulation time-ordered scheduling and execution of the VMs. Prior approaches such as time dilation are less efficient due to the high degree of multiplexing possible when multiple multi-core VMs are simulated on multi-core host systems. We present a new simulation time-ordered scheduler to efficiently schedule multi-core VMs on multi-core real hosts, with a virtual clock realized on each virtual core. The distinguishing features of our approach are: (1) customizable granularity of the VM scheduling time unit on the simulation time axis, (2) ability to take arbitrary leaps in virtual time by VMs to maximize the utilization of host (real) cores when guest virtual cores idle, and (3) empirically determinable optimality in the tradeoff between total execution (real) time and time-ordering accuracy levels. Experiments show that it is possible to get nearly perfect time-ordered execution, with a slight cost in total run time, relative to optimized non-simulation VM schedulers. Interestingly, with our time-ordered scheduler, it is also possible to reduce the time-ordering error from over 50% of non-simulation scheduler to less than 1% realized by our scheduler, with almost the same run time efficiency as that of the highly efficient non-simulation VM schedulers.
Keywords
clocks; multiprocessing systems; processor scheduling; virtual machines; VM scheduling time unit; customizable granularity; multicore guest virtual machine; multicore host; network simulation; nonsimulation scheduler; simulation time axis; simulation time-ordered scheduler; time-ordered execution; time-ordering error reduction; virtual clock; Clocks; Computational modeling; Emulation; Hardware; Instruction sets; Multicore processing; Virtual machine monitors;
fLanguage
English
Publisher
ieee
Conference_Titel
Principles of Advanced and Distributed Simulation (PADS), 2011 IEEE Workshop on
Conference_Location
Nice
ISSN
1087-4097
Print_ISBN
978-1-4577-1363-7
Electronic_ISBN
1087-4097
Type
conf
DOI
10.1109/PADS.2011.5936746
Filename
5936746
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