DocumentCode
1973979
Title
Design of a novel 8-port memory cell
Author
Chang, Jian ; Man, K.L. ; Lim, EngGee
Author_Institution
Texas Instrum., Dallas, TX, USA
fYear
2010
fDate
22-23 Nov. 2010
Firstpage
445
Lastpage
448
Abstract
A general procedure to calculate the stability of the multiport memory cell is proposed. Noise margins of the 4-port and 8-port SRAM cell are studied. A novel 8-port memory cell is proposed to reduce the read access time.
Keywords
SRAM chips; circuit stability; integrated circuit noise; multiport networks; 4-port SRAM cell; 8-port SRAM cell; 8-port memory cell design; multiport memory cell stability; noise margin; read access time reduction; Capacitance; Computer architecture; Inverters; Microprocessors; Noise; Random access memory; Transistors; multiport SRAM; noise margin;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2010 International
Conference_Location
Seoul
Print_ISBN
978-1-4244-8633-5
Type
conf
DOI
10.1109/SOCDC.2010.5682876
Filename
5682876
Link To Document