A 720Mbps fast auxiliary channel design for DisplayPort 1.2

Author

Jin, Hyun-Bae ; Han, Jong-Seok ; Kang, Jin-Ku

Author_Institution

Dept. of Electron. Eng., Inha Univ., Incheon, South Korea

fYear

2010

fDate

22-23 Nov. 2010

Firstpage

404

Lastpage

407

Abstract

This paper presents the design of a fast auxiliary channel bus for DisplayPort 1.2 interface. The fast auxiliary channel supports Manchester transactions at 1 Mbps and fast auxiliary transactions at 780 Mbps. The Manchester transaction is used for managing the main link and auxiliary channel and the fast auxiliary transaction is for data transfer via the auxiliary channel. Simplified serial bus architecture is proposed to be implemented in fast auxiliary channel. The fast auxiliary channel is synthesized using a FPGA board and it operates at 72 MHz to support 720 Mbps.

Keywords

data communication; system buses; DisplayPort 1.2 interface; FPGA board; Manchester transaction; data transfer; fast auxiliary channel bus; fast auxiliary channel design; fast auxiliary transaction; simplified serial bus architecture; Bandwidth; Encoding; Field programmable gate arrays; Payloads; Periodic structures; Random access memory; Training; DiplayPort; DisplayPort Configuration Data(DPCD); Extended Display Identification Data(EDID); Fast uxiliary channel (FAUX); Main link;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2010 International

Conference_Location

Seoul

Print_ISBN

978-1-4244-8633-5

Type

conf

DOI

10.1109/SOCDC.2010.5682886

Filename

5682886