Leakage reduction of sub-55nm SRAM based on a feedback monitor scheme for standby voltage scaling

Reducing standby supply voltage to DRV can sharply decrease leakage power. In this paper, a feedback monitor scheme for standby V_DD scaling is proposed. The feedback scheme utilizes the same memory cell to obtain exactly the same performance with SRAM core cells and thus to monitor approximate DRV tail of SRAM array. Based on Monte-Carlo DRV distribution along with its dependencies on body-bias and source-bias voltage, we add controlling options to regulate the DRV of monitor cells and then to approach the worst-case DRV of core cells. The feedback monitor scheme for detecting DRV is implemented with bank-based SRAM design. Simulation results on 55 nm CMOS process indicates that for a 512 KB SRAM, leakage power savings are achieved in different process corners compared to conventional SRAM structure.