Towards efficient on-chip sensor interconnect architecture for multi-core processors

With increasing number of cores in a SoC, the number of on-chip sensors to monitor temperature, voltage and soft errors is growing. Several researchers have suggested that even in multi-core/many-core era, the power and voltage management would still remain centralized. This necessitates an efficient channel to communicate sensor data towards the central control unhindered by the application data traffic or contending with it. Here, we propose an efficient fault tolerant tree based dedicated network to transmit the sensor data. Further, with the proposed architecture, router design becomes much simpler. Fault tolerance has been provided and synthesis results show that such fault tolerance is achieved at a very low area overhead ranging from 2.9% to 14.9% of the router area for the range of network parameters considered in this paper.