Design of probabilistic-based Markov Random Field logic gates in 65nm CMOS technology

As the VLSI technology node is getting into the sub-100 nm regime, the reliability issues caused by random interferences such as noise, process variations and manufacturing defects are changing the nature of digital computation from deterministic to probabilistic. This paper studies the principle of probabilistic-based Markov Random Field (MRF) design methodology for CMOS static logic gates. The MRF design technique is able to significantly improve the reliability and interference tolerance of the logic circuits. A Differential Cascode Voltage Switch (DCVS) based MRF logic design method is proposed, which presents substantial noise immunity improvement over the normal MRF logic circuits. The proposed method is validated by simulation in 65 nm CMOS technology.