DocumentCode :
1974856
Title :
An all digital time amplifier with interpolation scheme for low gain variation
Author :
Dhar, Debashis ; Kwak, Young-Ho ; Jung, Inhwa ; Kim, Chulwoo
Author_Institution :
Dept. of Electr. Eng., Korea Univ., Seoul, South Korea
fYear :
2010
fDate :
22-23 Nov. 2010
Firstpage :
276
Lastpage :
278
Abstract :
An all digital time amplifier (TA) is proposed in 0.13 μm CMOS process. The TA is based on quantization scheme; hence it guarantees large input range. An interpolation scheme is employed to achieve more than 2 times reduction in gain variation of the TA over the input range. The all digital TA is portable to other process technology with smaller design effort. The TA shows a gain variation of less than 5% and consumes a power of 14 mW.
Keywords :
CMOS digital integrated circuits; amplifiers; interpolation; CMOS process; all digital time amplifier; interpolation scheme; low gain variation; power 14 mW; quantization scheme; size 0.13 mum; CMOS integrated circuits; Clocks; Delay; Interpolation; Logic gates; MOS devices; Signal resolution; All Digital Time Amplifier; Interpolation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference (ISOCC), 2010 International
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-8633-5
Type :
conf
DOI :
10.1109/SOCDC.2010.5682917
Filename :
5682917
Link To Document :
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