A robust pulse delay circuit utilizing a differential buffer ring

In this paper, we propose a pulse delay circuit using a differential buffer ring. The proposed circuit keeps an input pulse propagating on the buffer ring without a degradation of pulse width information. The cross-coupled buffer ring with compensating inverters improves the tolerance to the process variation. The proposed circuit has been implemented using 65nm CMOS process, and the simulation results demonstrate that the proposed circuit keeps an input pulse width independent of the process corner conditions, and the measurement results show that the proposed pulse delay circuit using differential buffer ring is more robust to the process variability than conventional buffer ring.