DocumentCode
1975177
Title
Enhenced redundancy analysis for memories using geometric faults based search tree
Author
Kang, Wooheon ; Cho, Hyungjun ; Kang, Sungho
Author_Institution
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
fYear
2010
fDate
22-23 Nov. 2010
Firstpage
225
Lastpage
228
Abstract
With the growth of memory capacity and density, test cost and yield improvement are becoming more important. To increase yield of memory, redundancy analysis (RA) which analyzes the faults in memory is essential. However, the time for finding solutions to repair memories with faulty cells is very huge because most RA algorithms for automatic test equipment (ATE) are based on a tree structure. To reduce the time of memory test & repair is important to increase the memory yield using ATE. In order to reduce the time of memory test & repair, an RA algorithm with an early termination condition is proposed and it builds a geometric faults based search tree. To build the proposed algorithm, the faults in a memory are classified into geometric faults according to their characteristic. The experimental results show the effectiveness of the proposed algorithm.
Keywords
automatic test equipment; fault diagnosis; redundancy; search problems; semiconductor storage; storage management; trees (mathematics); automatic test equipment; early termination condition; enhanced redundancy analysis; faulty cells; geometric faults; memory capacity; memory density; memory test; memory yield; repair memories; search tree; test cost; tree structure; yield improvement; Algorithm design and analysis; Classification algorithms; Complexity theory; Maintenance engineering; Memory management; Redundancy; Resource management; ATE; Early termination conditions; RA algorithm; test & repair time;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2010 International
Conference_Location
Seoul
Print_ISBN
978-1-4244-8633-5
Type
conf
DOI
10.1109/SOCDC.2010.5682932
Filename
5682932
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