Integrator-chain multiplier

An MVL (multiple-valued-logic) multiplier circuit scheme, called the integrator-chain method, is presented. This circuit scheme is particularly suited to the switched-capacitor topology. The feasibility of circuit implementations of the integrator-chain multiplier design in various number systems, including the sign-bit number representation, the R´s and (R-1)´s complement representations, and the signed-digit-number (SDN) system, is discussed. It is demonstrated by simulation that a 4×4 multiplier circuit operating in a radix-7 SDN system has a size comparable to the simplest binary counterpart