• DocumentCode
    1975232
  • Title

    A new communication mechanism for multi-core systems in industrial design

  • Author

    Han, Gang ; Lu, Jia ; Li, Baoliang ; Wang, Junhui ; Wu, Guofu ; Dou, Wenhua

  • Author_Institution
    Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha, China
  • Volume
    2
  • fYear
    2012
  • fDate
    20-21 Oct. 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In industrial design, multi-core systems are receiving more and more attention for their special characteristics as low power consumption, reliability and extensibility. Multi-core processors are usually designed in shared memory architecture and tasks on different cores run concurrently. The communication between tasks must be performed consistently, which means the access to shared communication buffer (or resource) should be atomic. Many mechanisms have been proposed for this purpose, e.g. wait-free and lock-based. However, different mechanisms show different performance on system schedulability and memory overhead. So, it would be a good choice to combine these mechanisms together, i.e. to protect different resources with different mechanisms. This is a variation of bin-packing problem, which is NP-complete. We propose a heuristic algorithm to select the communication mechanisms with minimum memory requirements executing within the time constraints. The experiment demonstrates that the heuristic provides close to optimal solutions and the proposed algorithm can significantly reduce the memory consumption of wait-free method, guaranteeing that all tasks complete before their deadlines.
  • Keywords
    bin packing; buffer circuits; circuit reliability; computational complexity; heuristic programming; industrial engineering; optimisation; random-access storage; scheduling; shared memory systems; NP-complete; RAM memory; bin-packing problem; communication mechanism; extensibility; heuristic algorithm; industrial design; lock-based mechanism; memory overhead; multicore processor system; power consumption; reliability; schedulability; shared communication buffer; shared memory architecture; wait-free mechanism; Data communication; Memory management; Multicore processing; Protocols; Random access memory; Real-time systems; Time factors; automotive; data consistency; industrial design; optimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    System Science, Engineering Design and Manufacturing Informatization (ICSEM), 2012 3rd International Conference on
  • Conference_Location
    Chengdu
  • Print_ISBN
    978-1-4673-0914-1
  • Type

    conf

  • DOI
    10.1109/ICSSEM.2012.6340792
  • Filename
    6340792