Effective workload reduction for early-stage power estimation

In today´s information technology trends, all kinds of digital and multimedia technologies are converging into single mobile internet devices (MID). This digital convergence trend is being accelerated by deep sub-micron technology and the concept of system-on-chip design. In SoC design, reconfigurable soft-IPs are widely used than the hard-IPs to obtain more optimized design toward a system or platform. To decide optimized configuration of the soft-IPs, early-stage design exploration is required. Also, choosing appropriate workloads and workload reduction methodology are very crucial for accurate and fast estimation in design exploration. In this paper, we propose a methodology to reduce the amount of workloads used for early-stage power estimation. We explore two scenarios in our analysis for effective workload reduction: (i) instruction-distribution-based workload reduction; (ii) demand-based workload reduction. Based on our experiment, power estimation with the reduced-workload shows more accurate and faster than with conventional reduction method (Simpoint). We conclude that workload reduction technologies which are customized for demanded performance metric are highly required for effective and faster performance evaluation at each design stage - especially in SoC design.