High-Level Power Estimation of FPGA

With the success of battery-based personal computing devices and wireless communication systems, low power has become a key issue in embedded system design. As a result, designers are now encouraged to consider the impact of their decisions not only on speed and area performances, but also on power consumption throughout the entire design process. This paper presents our contribution in terms of power estimation and exploration methodology based on high-level power modeling approach of re-configurable devices such as field-programmable gate arrays (FPGA). In order to address the different abstraction levels and the various targets, a global methodology is proposed here to elaborate suitable models. With our high-level power model, the FPGA power estimation can be obtained at early stage of the design process. Experimental results indicate on a classical signal-processing algorithm; that the gap between measures and estimations is lower than 18%. From these models, several consumption optimizations can be deducted from the sensitivity metric.