Title :
Novel ternary logic design based on CNFET
Author :
Nan, Haiqing ; Choi, Ken
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
Abstract :
As CMOS technology is scaled down, transistor density of a chip is increased dramatically, which results in the increasing of the complexity of interconnections. In this paper, a novel design of ternary logic based on carbon nanotube FETs (CNFETs) is proposed and compared with the previous CNFET-based ternary logic designs. Especially, in the proposed CNFET-based ternary logic design, different back biasing voltages and diameters of CNFETs are effectively used to achieve ultra-low power consumption. Extensive simulation results using HSPICE are reported to show that the proposed CNFET-based ternary logic gate reduces leakage current and power delay product (PDP) multiple orders of magnitude compared to the previous CNFET-based ternary logic designs.
Keywords :
carbon nanotubes; field effect transistors; logic design; logic gates; nanotube devices; ternary logic; C; CNFET; HSPICE; carbon nanotube FET; power delay product; ternary logic design; ternary logic gate; CNTFETs; Delay; Inverters; Leakage current; Multivalued logic; Resistors; Threshold voltage; CNFET; MVL; interconnection; ternary logic;
Conference_Titel :
SoC Design Conference (ISOCC), 2010 International
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-8633-5
DOI :
10.1109/SOCDC.2010.5682960