Power gated SRAM circuits with data retention capability and high immunity to noise: A comparison for reliability in low leakage sleep mode

Author

Jiao, Hailong ; Kursun, Volkan

Author_Institution

Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China

fYear

2010

fDate

22-23 Nov. 2010

Firstpage

5

Lastpage

8

Abstract

A new power gated 6T SRAM circuit is proposed in this paper to suppress leakage power consumption in data retention SLEEP mode. A new write assist circuitry is presented to enhance the write margin of the new power gated memory circuit. Design tradeoffs among data stability, power consumption, and write margin are evaluated with different SRAM circuits. The leakage power consumption is reduced by up to 3.84× and the read static noise margin is increased by up to 4.79× with the new memory power gating technique as compared to a previously published power gated 6T SRAM circuit in a UMC 80nm CMOS technology.

Keywords

CMOS memory circuits; SRAM chips; integrated circuit reliability; leakage currents; CMOS technology; UMC; data retention SLEEP mode; data retention capability; data stability; design tradeoffs; low leakage sleep mode; memory power gating technique; power gated SRAM circuits; power gated memory circuit; read static noise margin; reliability; size 80 nm; suppress leakage power consumption; write assist circuitry; write margin; Arrays; Circuit stability; Inverters; Logic gates; Power demand; Random access memory; Transistors; Power gating; cache; data stability; leakage power consumption; single-ended write; write assist circuitry;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2010 International

Conference_Location

Seoul

Print_ISBN

978-1-4244-8633-5

Type

conf

DOI

10.1109/SOCDC.2010.5682988

Filename

5682988