Evaluation of IBIS modelling techniques for signal integrity simulations without and with package parasitics

Author

Ji, Yuancheng ; Mouthaan, Koen ; Venkatarayalu, Neelakantam V.

Author_Institution

Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore, Singapore

fYear

2010

fDate

7-9 Dec. 2010

Firstpage

1

Lastpage

4

Abstract

Input/Output Buffer Information Specification (IBIS) models are widely used in signal integrity analysis because of their ability to protect proprietary information and to reduce simulation time when compared to full SPICE simulations. Generation of IBIS models with I/V and V/T data from a full SPICE model of a typical digital buffer without and with package parasitics is investigated in this paper. Several different IBIS model generation strategies to incorporate package effects are validated with the full SPICE model in order to provide a suitable approach. In addition, the accuracy of IBIS simulations in HSPICE and ADS is investigated.

Keywords

SPICE; buffer circuits; circuit simulation; digital circuits; electronics packaging; ADS; HSPICE; I/V data; IBIS modelling technique; V/T data; digital buffer; full SPICE model; input-output buffer information specification model; package parasitics; signal integrity simulation; Accuracy; Analytical models; Data models; Integrated circuit modeling; Interpolation; SPICE; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE

Conference_Location

Singapore

ISSN

2151-1225

Print_ISBN

978-1-4244-9068-4

Electronic_ISBN

2151-1225

Type

conf

DOI

10.1109/EDAPS.2010.5683003

Filename

5683003