Title :
2k nonvolatile shadow RAM and 256k EEPROM SONOS nonvolatile memory development
Author :
Nasby, R.D. ; Murray, J.R. ; Habermehl, S.D. ; Bennett, R.S. ; Tafoya-Porras, B.C. ; Mahl, P.R. ; Rodriguez, J.L. ; Jones, R.V. ; Knoll, M.G.
Author_Institution :
Sandia Nat. Labs., Albuquerque, NM, USA
Abstract :
This paper describes SONOS nonvolatile memory development at Sandia National Laboratories. A 256 kbit EEPROM nonvolatile memory and a 2 kbit nonvolatile shadow RAM are under development using an n-channel CMOS/SONOS (complementary metal oxide semiconductor/silicon oxide nitride oxide semiconductor) memory technology. The technology has 1.2 μm minimum features in a twin well design using shallow trench isolation
Keywords :
CMOS memory circuits; EPROM; dielectric thin films; elemental semiconductors; integrated circuit design; integrated circuit testing; random-access storage; silicon; 1.2 micron; 2 kbit; 256 kbit; EEPROM; EEPROM nonvolatile memory; SONOS nonvolatile memory; SONOS nonvolatile memory development; Si; Si-SiO2-Si3N4-SiO2-Si; feature size; n-channel CMOS silicon-oxide-nitride-oxide-semiconductor memory; nonvolatile shadow RAM; shallow trench isolation; twin well design; Circuits; Clocks; EPROM; Laboratories; Nonvolatile memory; Random access memory; Read-write memory; SONOS devices; Strontium; Threshold voltage;
Conference_Titel :
Nonvolatile Memory Technology Conference, 1998. 1998 Proceedings. Seventh Biennial IEEE
Conference_Location :
Albuquerque, NM
Print_ISBN :
0-7803-4518-5
DOI :
10.1109/NVMT.1998.723208
