The design and implementation of a multiqueue buffer for VLSI communication switches

Author

Frazier, Gregory L. ; Tamir, Yuval

Author_Institution

Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA

fYear

1989

fDate

2-4 Oct 1989

Firstpage

466

Lastpage

471

Abstract

The micro-architecture and VLSI implementation of a dynamically allocated multiqueue (DAMQ) buffer are presented. Design tradeoffs for the DAMQ buffer´s datapath are discussed and a floorplan and the timing of the major functional units are presented. It is shown that in VLSI switches, with buffers than can store multiple packets, additional chip area is better used for the control of DAMQ buffers than for increased buffer space in simpler FIFO buffers

Keywords

VLSI; buffer storage; circuit layout CAD; memory architecture; DAMQ buffers; VLSI communication switches; additional chip area; datapath; dynamically allocated multiqueue buffer; floorplan; functional units; micro-architecture; multiple packets; timing; Buffer storage; Communication switching; Computer science; Coprocessors; Delay; Multiprocessor interconnection networks; Packet switching; Switches; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-1971-6

Type

conf

DOI

10.1109/ICCD.1989.63410

Filename

63410

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1977354