DocumentCode
1977548
Title
Design of a true single-phase-clock divider in 0.13µm CMOS
Author
Wang, Lei ; Xiong, Yong-Zhong ; Hu, San-Ming ; Lim, Teck-Guan
Author_Institution
Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
fYear
2010
fDate
7-9 Dec. 2010
Firstpage
1
Lastpage
4
Abstract
The design of a true single-phase-clock (TSPC) divider with a division ratio of 8 in 0.13μm BiCMOS technology is presented. Through the careful layout design, the divider is able to operate up to 7.5GHz with the dc voltage supply of 1.8V. The core circuit size is only 80×20μm2.
Keywords
BiCMOS digital integrated circuits; CMOS digital integrated circuits; clocks; field effect MMIC; frequency dividers; integrated circuit layout; BiCMOS technology; TSPC divider; frequency 7.5 GHz; layout design; size 0.13 mum; true single-phase-clock divider; voltage 1.8 V; CMOS integrated circuits; Frequency conversion; Frequency measurement; Inverters; Layout; MOS devices; Metals;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE
Conference_Location
Singapore
ISSN
2151-1225
Print_ISBN
978-1-4244-9068-4
Electronic_ISBN
2151-1225
Type
conf
DOI
10.1109/EDAPS.2010.5683039
Filename
5683039
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